LogicFab has developed a seven stage state-of-the-art verification flow capable of verifying the product from the chip architecture to the final Product.
LogicFab Semiconductors has a best world class Verification engineers Team. The team has verified many SoC’s, and defined a methodology to Guarantee the “First Time Right Silicon”.
The first task in verification is defining and organizing the correct verification inputs. The seven stage verification flow defines the input and the verification goal of each stage.
The team has expertise in doing verification using the latest verification methodology like VMM, OVM.
LogicFab major expertise areas are defined below :
UsDefining the Verification strategy
Re-usable Verification IP Creation
System level Verification
Timing Verification
Formal VerificationGo
VERIFICATION IP DEVELOPMENT
Verification Environment
DevelopmentSystem modelling
Bus functional model development
Protocol monitors and checkers
System Verilog Migration
System Verilog, SystemC, Verilog,
VHDL, C, C++, TCL, PERL,
MATLAB, VMM, OVM, SpecMAN,
Vera
